This invention relates to polishing methods and apparatus and more particularly, to such methods and apparatus for accurately polishing wafers of semiconductor material with high throughput and in a manner compatible with semiconductor processing clean room environments.
The production of integrated circuits begins with the creation of high quality semiconductor wafers. Each wafer is of relatively high cost due to the detailed processing needed to produce it. During the integrated circuit production process, an extremely flat surface is desired on at least one face of the wafer. Wafer polishing to achieve such a flat surface is a known technique.
Such polishing generally includes attaching one side of the wafer to a flat surface of a wafer carrier or chuck and pressing the wafer against a flat polishing surface. The polishing surface is moved under the wafer, and the wafer may also be rotated about its vertical axis and oscillated back and forth to improve polishing action. The polishing surface is generally a pad attached to a rigid flat table which is rotated to provide movement and onto which an abrasive and/or chemical slurry is pumped. The joint functions of the pad, the slurry, and the relative movements of the components produces a combined mechanical and chemical process at the wafer surface which produces a highly flat surface on a wafer where surface variations are kept to less than, for example, 0.5 .mu.m.
Polishing has typically been performed prior to integrated circuit fabrication so that a flat surface is available on the semiconductor wafer on which the circuit fabrication can take place. As integrated circuits increase in complexity, the conductive line widths have reduced considerably, making the focus and depth of field of the imaging process more sensitive to surface variations on the substrate. This has increased the desire for wafers with improved surfaces. Further during the integrated circuit fabrication process, layers of, for example, conductors and dielectrics, are built up on the wafer, on top of which other such layers are to be created. Thus, it has become necessary to "re-flatten" the wafer surface during the actual fabrication of the integrated circuit and not merely before it. The act of re-flattening is referred to as planarization. At each successive one of several planarization operations the wafer is considerably more valuable. Given semiconductor processing costs, it is quite possible that a single 8" partially processed wafer is worth $10,000 or more when planarization is performed. Great care in handling of each such wafer is obviously required.
Speed of wafer polishing has always been of interest but has become more important when planarization is one of the necessary sequential processing steps. Prior arrangements, typically, polish one or two wafers, with substantial waiting time to load and unload wafers. Methods and apparatus are needed to speed up the polisher process.
The increase in value of the wafers being polished has greatly increased the need for precision in the planarization process. Improper polishing of a wafer worth $100 is a completely different matter than improperly polishing one worth $10,000. Methods and apparatus are needed to provide improved polishing, particularly in a rapid production environment.
These needs are met by the present invention.